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We are seeking a seasoned Physical Design technical leader with deep expertise in high-performance & low-power design. In this highly visible role, you will work closely with cross-functional teams to come up with efficient chip and IP physical architecture taking into account physical design constraints early in the design cycle.

• You will be responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off.
• You will also collaborate to drive methodologies and “best-known methods” to streamline PD work and develop guidelines and checklists.
• You will be the primary technical contact for your focus area and are motivated to solve more challenging timing closure issues, area & power optimization etc.