Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.

In this role, you will work closely with the RFIC design team to layout and verify custom RF and analog IP for complex SoC products.

As a RF layout engineer, you will be responsible for
– Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.
– Block level and top-level layout through full verification flow including extraction, DRC, LVS, and DFM checking
– Co-work with designers on block level and top-level floorplanning
– Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling
– Top-level layout integration and verification, schedule management

BS and 3+ years of relevant industry experience.