Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth.

In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy

Participate in Cache micro architecture development from specifications found from architecture guideline and model analysis.

Explore architecture trade-offs in system performance, area, and power consumption along with the performance analysis team.

Develop/debug RTL design of different sections of the cache.

Work with physical design team to close timing of the same.