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In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC using state of the art process technology.

• Work with design teams to understand and debug constraints, facilitate logic changes to improve timing.
• Work with Physical Design team highlighting issues and best practices.
• Help create timing ECOs for project tapeout.
• Create and maintain scripts and methodologies for analysis and runs.
• Create documentation and help with guidelines/specs.
• Deep analysis of timing paths to identify key issues.
• Implement timing infrastructure