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In this highly visible role, you will be at the center of a chip design effort collaborating with many teams, with a critical impact on getting functional products to millions of customers quickly. We are looking for a strong candidate to join our processor verification team focusing on Power Management and Clock Control verification.

As a Processor Power Management Verification Engineer, you will have the responsibilities as follows:
– Work closely with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic
– Develop and execute test plans and schedules for the power management and clock control logic.
– Develop tests in Assembly, Scripts, System Verilog, or vectors according to test plans to drive testing in simulation and emulation environments
– Root cause failures and propose potential solution to the design team.
– Work with silicon bringup team on developing tests that work in the emulation and FPGA environments. Aid silicon debug in related part of the design.
– Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered
– Develop checkers or Verilog/System Verilog-base transactor to verify the design
– Write assertions and apply formal verification to the design