Come and join the team that crafted the M3/M4! Apple makes the greatest SoCs in the world; to do that takes thousands of employees, multiple years and very significant R&D spending. To make the best use of those employees, time, and money requires excellent methodologies and structures. As we continue to expand and mature, the processes used to develop these SOCs must be improved. Join us to do your life’s best work in this rare opportunity to help define the next big thing that will surprise and delight the world!

As a SoC DRAM Memory Subsystem Validation and Debug Program Manager, you will drive the memory subsystem readiness for our custom SoCs. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. Your charter will include managing bring-up, validation, and the complicated debug of our groundbreaking memory subsystem. You will also help craft the DRAM industry’s mobile roadmap and drive innovative DRAM technologies to accompany SoC’s across Apple’s product lines. In this multifaceted role, you will be the critical interface between Apple’s DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering and software teams to ensure these advanced memory technologies are delivered from architecture to mass production to Apple’s industry leading quality standards.

• Work on an impactful EPM team responsible for driving technical issue resolution to enable timely silicon to meet daring product schedules.
• Make detailed program level plans for memory feature roll-out and align multi-functional teams on the support and validation plans.
• Interface and drive memory related silicon issues across multi-functional teams: Design, Verification, Silicon Validation, Productization, System Hardware and Software.
• Drive debug activities in post silicon environments, root-cause problems, and steer the team to the best corrective action to move forward.
• Focused issue reporting, bug tracking, organizing and reporting of program risks and status at an executive level.
• Plan and lead adoption of DRAM technologies, custom package development and qualification process with multi-functional teams.
• Work closely with the DRAM Global Supply Management (GSM), DRAM & Package Engineering and SoC Program Management organizations to set priorities.
• Attend and drive technical sessions with DRAM vendors on new DRAM technology development to track and follow-up issues/action items and drive vendors to meet spec and schedule requirements.
• Work with DRAM GSM and silicon material management teams to plan and track distribution of new DRAM material across all systems in development.
• Enable tight collaboration between Design for Test (DFT), Product/Test/QA engineering, SiVal and Systems teams during NPI to finalize SoC performance targets and screen requirements.
• Drive internal program process to guarantee high quality silicon execution.

BS + 10 years of relevant experience.Prior experience in SOC DRAM Memory Design, Validation, Architecture or Test/Product Engineering.