Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? Imagine the delight in knowing your efforts were critical in the implementation of system-on-chip (SoC) designs in the next generation of Apple products!

In this exciting role, you will develop, maintain, and enhance logic equivalence checking flows. You will architect, design, and implement the software and methodologies that design teams use to verify designs and complete ECOs. You will develop, maintain, and enhance machine learning and generative AI solutions to improve logic equivalence flows. You will work directly with EDA vendors to design new tool features, and you will directly own logic equivalence signoff on tape outs.

In this highly visible role, your primary responsibilities will include:

– Developing, maintaining, and enhancing CAD applications for logical equivalence.

– Supporting frontend design closure , ECO verification, and flow signoff.

– Triaging and solving CAD flow problems, and working around EDA tool problems.

– Working directly with EDA vendors to resolve tool issues, and identifying enhancements.

– Working directly with EDA vendors to architect new tool features and methodologies.

– Collaborating with other CAD engineers, including synthesis, DV, analytics, and signoff to build integrated flows.

– Participating and engaging with cross functional teams to tackle key logic equivalence challenges.

– Using ML and GenAI based solutions to improve CAD applications.

Experience with ASIC Design EDA Tools, CAD flows, and/or ASIC design methodologies.Knowledge of Tcl, Python or Perl scripting languages.Knowledge of Verilog or SystemVerilog coding for hardware design or verification.Minimum requirement of BS and 3+ years of relevant industry experience.