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As a CPU CDC/STA Engineer, you will play a major role analyzing the design and driving fixes as well as developing, maintaining and improving our Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites.

In this role, you will be:

• Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs
• Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions
• Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for our CPUs
• Responsible for debugging vendor tool problems and collaborate with designers to help solve their problems
• Working closely with EDA vendor representatives to drive improvements and new methodologies
• Working closely with RTL, Verification, CAD, and Physical Design teams

Minimum BS and 3+ years of relevant industry experienceScripting skills in Tcl or PerlExperience in one or more of the following: Static Timing Analysis (STA), Clock-Domain Crossing (CDC), or Reset Domain Crossing (RDC) solutionsExperience in Verilog